#include <csl_bootcfgaux.h>
#include <cslr_emif4f.h>
#include <cslr_cgem.h>
#include <csl_bootrom.h>
#include "KeyStone_DDR_Init.h"

#if 0

#define CSL_BOOT_ROM_DDR3_REGS        (0x00883500)
CSL_RomcfgRegs   * boot_rom_ddr3_regs = (CSL_RomcfgRegs *) CSL_BOOT_ROM_DDR3_REGS;

void _c_int00()
{    

		  float clock_MHz = 500;
         CSL_BootCfgUnlockKicker();	
         boot_rom_ddr3_regs->Enable_bitmap = 0xFF607A;
		//boot_cfg_regs->DDR3_CONFIG_REG[23] |= 0x00000200; //Set bit 9 = 1 to use forced ratio leveling for read DQS
		//boot_cfg_regs->DDR3_CONFIG_REG[23] &= ~(0x00000200); //Clear bit 9 = 1 to use full auto leveling + incremental leveling

		/*the PHY_RESET is pulsed (0 -> 1 -> 0) to latch these
		leveling configuration values into the PHY logic.*/
		boot_rom_ddr3_regs->Phy_ctrl_1 &= ~(0x00008000);
		boot_rom_ddr3_regs->Phy_ctrl_1 |= (0x00008000);
		boot_rom_ddr3_regs->Phy_ctrl_1 &= ~(0x00008000);


		/*Drives CKE low.
		This is a JEDEC requirement that we have 500us delay between reset de-assert
		and cke assert and then program the correct refresh rate
		The DDR internal clock is divide by 16 before SDCFG write*/
		boot_rom_ddr3_regs->Refresh_ctl = 0x80000000|(unsigned int)(500.f*clock_MHz/16.f);

		boot_rom_ddr3_regs->Timing_1 =
			((unsigned int)(15*clock_MHz/1000.f-0.0001f)<<CSL_EMIF4F_SDRAM_TIM_1_REG_T_RP_SHIFT)|
			((unsigned int)(15*clock_MHz/1000.f-0.0001f)<<CSL_EMIF4F_SDRAM_TIM_1_REG_T_RCD_SHIFT)|
			((unsigned int)(15*clock_MHz/1000.f-0.0001f)<<CSL_EMIF4F_SDRAM_TIM_1_REG_T_WR_SHIFT)|
			((unsigned int)(36*clock_MHz/1000.f-0.0001f)<<CSL_EMIF4F_SDRAM_TIM_1_REG_T_RAS_SHIFT)|
			((unsigned int)(49.5*clock_MHz/1000.f-0.0001f)<<CSL_EMIF4F_SDRAM_TIM_1_REG_T_RC_SHIFT)|
			((unsigned int)(30*clock_MHz/4000.f-0.0001f)<<CSL_EMIF4F_SDRAM_TIM_1_REG_T_RRD_SHIFT)|	/*T_RRD = (tFAW/(4*tCK)) C 1*/
			(_max2(4-1, (unsigned int)(7.5*clock_MHz/1000.f-0.0001f))<<CSL_EMIF4F_SDRAM_TIM_1_REG_T_WTR_SHIFT);
		boot_rom_ddr3_regs->Timing_2	=
			(_max2(3-1, (unsigned int)(6*clock_MHz/1000.f-0.0001f))<<CSL_EMIF4F_SDRAM_TIM_2_REG_T_XP_SHIFT)|
			(_max2(5-1, (unsigned int)((110+10)*clock_MHz/1000.f-0.0001f))<<CSL_EMIF4F_SDRAM_TIM_2_REG_T_XSNR_SHIFT)|	/*T_XSNR = (tXS /tCK)C 1*/
			((512-1)<<CSL_EMIF4F_SDRAM_TIM_2_REG_T_XSRD_SHIFT)| 	/*T_XSRD =tXSDLLC 1*/
			(_max2(4-1, (unsigned int)(7.5*clock_MHz/1000.f-0.0001f))<<CSL_EMIF4F_SDRAM_TIM_2_REG_T_RTP_SHIFT)|
			(_max2(3-1, (unsigned int)(5.625*clock_MHz/1000.f-0.0001f))<<CSL_EMIF4F_SDRAM_TIM_2_REG_T_CKE_SHIFT);
		boot_rom_ddr3_regs->Timing_3	=
			(5<<CSL_EMIF4F_SDRAM_TIM_3_REG_T_PDLL_UL_SHIFT)|	/*This field must always be programmed to 0x5.*/
			((5)<<CSL_EMIF4F_SDRAM_TIM_3_REG_T_CSTA_SHIFT)| 	/*This field should be set according to PHY requirements as 0x5.*/
			((unsigned int)(5.625*clock_MHz/1000.f+0.9999f)<<CSL_EMIF4F_SDRAM_TIM_3_REG_T_CKESR_SHIFT)|
			((64-1)<<CSL_EMIF4F_SDRAM_TIM_3_REG_ZQ_ZQCS_SHIFT)|
			((unsigned int)(110*clock_MHz/1000.f-0.0001f)<<CSL_EMIF4F_SDRAM_TIM_3_REG_T_RFC_SHIFT)|
			(15<<CSL_EMIF4F_SDRAM_TIM_3_REG_T_RAS_MAX_SHIFT);	/*This field must always be programmed to 0xF.*/

	boot_rom_ddr3_regs->Phy_ctrl_1  = 0x00100100|
			(16<<CSL_EMIF4F_DDR_PHY_CTRL_1_REG_READ_LATENCY_SHIFT); 	/*between CAS Latency + 1 and CAS Latency + 7*/

		boot_rom_ddr3_regs->Zq_config =
			((0)<<CSL_EMIF4F_ZQ_CONFIG_REG_ZQ_CS1EN_SHIFT)|
			((1)<<CSL_EMIF4F_ZQ_CONFIG_REG_ZQ_CS0EN_SHIFT)|
			((1)<<CSL_EMIF4F_ZQ_CONFIG_REG_ZQ_DUALCALEN_SHIFT)| 	/*This bit should always be set to 1.*/
			((1)<<CSL_EMIF4F_ZQ_CONFIG_REG_ZQ_SFEXITEN_SHIFT)|
			((512/256-1)<<CSL_EMIF4F_ZQ_CONFIG_REG_ZQ_ZQINIT_MULT_SHIFT)|	/*T_ZQ_ZQINIT_MULT = (tZQinit/tZQoper C 1)*/
			((256/64-1)<<CSL_EMIF4F_ZQ_CONFIG_REG_ZQ_ZQCL_MULT_SHIFT)|	/*T_ZQ_ZQCL_MULT = (tZQoper/tZQCS C 1)*/
			/*interval between ZQCS commands = 0.5%/((TSens x Tdriftrate) + (VSens x Vdriftrate))
			=0.5%/((max (dRTTdT, dRONdTM) x Tdriftrate in C/second) + (max(dRTTdV, dRONdVM) x Vdriftrate in mV/second))
			this time need be converted to refresh period number*/
			((151515151/(64000000/8192))<<CSL_EMIF4F_ZQ_CONFIG_REG_ZQ_REFINTERVAL_SHIFT);

		/*map priority 0,1,2,3 to COS0,
		map priority 3,5,6,7 to COS1*/
		boot_rom_ddr3_regs->Pri_cos_map =
			((1)<<CSL_EMIF4F_PRI_COS_MAP_REG_PRI_COS_MAP_EN_SHIFT)|
			((1)<<CSL_EMIF4F_PRI_COS_MAP_REG_PRI_7_COS_SHIFT)|
			((1)<<CSL_EMIF4F_PRI_COS_MAP_REG_PRI_6_COS_SHIFT)|
			((1)<<CSL_EMIF4F_PRI_COS_MAP_REG_PRI_5_COS_SHIFT)|
			((1)<<CSL_EMIF4F_PRI_COS_MAP_REG_PRI_4_COS_SHIFT)|
			((0)<<CSL_EMIF4F_PRI_COS_MAP_REG_PRI_3_COS_SHIFT)|
			((0)<<CSL_EMIF4F_PRI_COS_MAP_REG_PRI_2_COS_SHIFT)|
			((0)<<CSL_EMIF4F_PRI_COS_MAP_REG_PRI_1_COS_SHIFT)|
			((0)<<CSL_EMIF4F_PRI_COS_MAP_REG_PRI_0_COS_SHIFT);

		/*master based COS map is disabled*/
		boot_rom_ddr3_regs->Mst_id_cos_map_1= 0;
		boot_rom_ddr3_regs->Mst_id_cos_map_2= 0;

		/*LAT_CONFIG*/
		boot_rom_ddr3_regs->Irq_enable=  //???
			(8<<CSL_EMIF4F_VBUSM_CONFIG_REG_COS_COUNT_1_SHIFT)|
			(16<<CSL_EMIF4F_VBUSM_CONFIG_REG_COS_COUNT_2_SHIFT)|
			(32<<CSL_EMIF4F_VBUSM_CONFIG_REG_PR_OLD_COUNT_SHIFT);

		boot_rom_ddr3_regs->Ecc_ctrl =
			((0)<<CSL_EMIF4F_ECC_CTRL_REG_ECC_EN_SHIFT)|
			((0)<<CSL_EMIF4F_ECC_CTRL_REG_ECC_ADDR_RNG_PROT_SHIFT)|
			((0)<<CSL_EMIF4F_ECC_CTRL_REG_ECC_ADDR_RNG_2_EN_SHIFT)|
			((0)<<CSL_EMIF4F_ECC_CTRL_REG_ECC_ADDR_RNG_1_EN_SHIFT);

		boot_rom_ddr3_regs->Ecc_addr_rng_1=
			((0)<<CSL_EMIF4F_ECC_ADDR_RNG_1_REG_ECC_STRT_ADDR_1_SHIFT)|
			((0)<<CSL_EMIF4F_ECC_ADDR_RNG_1_REG_ECC_END_ADDR_1_SHIFT);

		boot_rom_ddr3_regs->Ecc_addr_rng_2=
			((0)<<CSL_EMIF4F_ECC_ADDR_RNG_2_REG_ECC_STRT_ADDR_2_SHIFT)|
			((0)<<CSL_EMIF4F_ECC_ADDR_RNG_2_REG_ECC_END_ADDR_2_SHIFT);

		/* enables DRAM configuration.	It still has the refresh interval
		programmed to the longer number needed during DRAM initialization.*/
		boot_rom_ddr3_regs->Refresh_ctl = (unsigned int)(500.f*clock_MHz/16.f); //???

		boot_rom_ddr3_regs->config =
			(3<<CSL_EMIF4F_SDRAM_CONFIG_REG_SDRAM_TYPE_SHIFT)|	/*Set to 3 for DDR3. All other values reserved.*/
			(0<<CSL_EMIF4F_SDRAM_CONFIG_REG_IBANK_POS_SHIFT)|
			(DDR_TERM_RZQ_OVER_6<<CSL_EMIF4F_SDRAM_CONFIG_REG_DDR_TERM_SHIFT)|
			(DDR_DYN_ODT_OVER_4<<CSL_EMIF4F_SDRAM_CONFIG_REG_DYN_ODT_SHIFT)|
			(0<<CSL_EMIF4F_SDRAM_CONFIG_REG_DDR_DISABLE_DLL_SHIFT)|
			(SDRAM_DRIVE_RZQ_OVER_6<<CSL_EMIF4F_SDRAM_CONFIG_REG_SDRAM_DRIVE_SHIFT)|
			(DDR_CWL_7<<CSL_EMIF4F_SDRAM_CONFIG_REG_CWL_SHIFT)|
			(DDR_BUS_WIDTH_64<<CSL_EMIF4F_SDRAM_CONFIG_REG_NARROW_MODE_SHIFT)|
			(DDR_CL_10<<CSL_EMIF4F_SDRAM_CONFIG_REG_CL_SHIFT)|
			(DDR_ROW_SIZE_14_BIT<<CSL_EMIF4F_SDRAM_CONFIG_REG_ROWSIZE_SHIFT)|
			(DDR_BANK_NUM_8<<CSL_EMIF4F_SDRAM_CONFIG_REG_IBANK_SHIFT)|
			(0<<CSL_EMIF4F_SDRAM_CONFIG_REG_EBANK_SHIFT)|
			(DDR_PAGE_SIZE_10_BIT_1024_WORD<<CSL_EMIF4F_SDRAM_CONFIG_REG_PAGESIZE_SHIFT);
	
	//	for(i=0;i<100000;i++)
	//		asm(" nop");	//Wait 600us for HW init to complete
	

		boot_rom_ddr3_regs->Refresh_ctl	= (unsigned int)64000.f*clock_MHz/8192.f;//F42//0x02620414
	
		CSL_BootCfgLockKicker();
}

#endif
